High-speed and high-resolution electronic systems, such as high definition video systems, progressively require faster and more accurate conversion of signals from digital form to analog form. At higher speeds, it becomes more difficult to sustain linearity between the digital input signal and the analog output because of conversion errors introduced by the current switches of the DAC. Various approaches, based on p-channel MOSFET devices, have been suggested to improve the high speed performance of current switches used in DACs. In general, these approaches utilize a current cell that includes a p-channel MOSFET current source and two p-channel MOSFET steering transistors, each of which is capable of conducting the current made available by the current source. One steering transistor has its drain grounded. The other steering transistor, commonly known as the output transistor, has its drain connected to a current summing line of the DAC, the current of which represents the analog value of the digital input signal. A binary signal is applied to each current switch and circuitry is provided so that the binary signal is used to select one of the two transistors in the current cell for conduction of the current. If the output steering transistor is selected, the current from the current switch is combined on the current summing lines with the currents output by other current switches in the accumulation of an analog output proportional to the digital input signal. If the other steering transistor is selected, the current of the current switch is shunted and does not contribute to the total current on the current summing line.
One approach is represented by the current switch described in U.S. Pat. No. 4,831,282, entitled "CMOS INPUT CIRCUIT", issued to Joseph H. Colles on May 16, 1989. In this case, a biasing voltage controlled within precise limits is applied to the gate of the output steering transistor to reduce transient effects due to switching of the steering transistors in each current cell, thereby improving the accuracy of DACs.
A different type of current cell is described in an article by Y. Nakamura et al., entitled "A 10-b 70-MS CMOS D/A Converter", IEEE Journal of Solid-State Circuits, V26, N4, pp. 637-642, April 1991. The current cell includes three p-channel MOSFET transistors, one of which is a current source and the other two of which are steering transistors. The steering transistors are driven in phase opposition. Nakamura et al. observe that arrays of such current cells suffer graded and symmetrical errors and propose various measures to reduce the integral linearity error caused by these error distributions across the array.
Despite the development of these techniques, need still remains for a simple yet effective way to improve the high speed performance of DACs. One problem that arises in DACs is ringing of output analog signal.